 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| DATA SHEET BIPOLAR ANALOG INTEGRATED CIRCUIT PC1830 FILTER-CONTAINING VIDEO CHROMA, SYNCHRONIZING SIGNAL PROCESSING LSI COMPATIBLE WITH NTSC/PAL SYSTEM DESCRIPTION The PC1830 is a filter-containing video chroma, synchronizing signal processing LSI compatible with the NTSC/ PAL system. A decoder which converts composite video or separate Y/C video signals into a brightness signal and a color difference signal and outputs the result, and a matrix which comprises independent brightness signal/color difference signal input pins are integrated on one chip. Decoder output can be used to drive an A/D converter; it is appropriate for picture-in-picture screen signal processing and multimedia boards. FEATURES * Contains a trap filter, band-pass filter, delay line, and color difference output low-pass filter. Peripheral parts can be drastically reduced. * Low power consumption Appropriate for use with digital boards because of 5-V single power supply operation. * DC control for user adjustment pins Centralized control can be performed by a microcontroller. * One chip compatible with both NTSC and PAL systems Boards common to NTSC and PAL systems can be easily constructed. * S pin input Supports composite and separate Y/C video signal inputs. * Demodulation ratio/demodulation angle change (matrix) Demodulation ratio/demodulation angle can be selected in response to the NTSC or PAL system. * Contains color difference tint control Fine adjustment of the demodulation axis can be made for both the NTSC and PAL systems. ORDERING INFORMATION Part Number Package 42-pin plastic shrink SOP (375 mil) PC1830GT The information in this document is subject to change without notice. Document No. S11146EJ4V0DS00 (4th edition) Date Published April 1998 N CP(K) Printed in Japan The mark shows major revised points. (c) 1994 PC1830 1. SYSTEM BLOCK DIAGRAM VIDEO CAPTURE SYSTEM BLOCK DIAGRAM NTSC PAL 3.58 4.43 HD VD BLK Clamp pulse CLP 8-bit A/D PC659A 8 910 fH H lock clock generator 8-bit A/D PC659A 8 Divider 2 Digital video (RGB or YUV) signal output Composite video or Y/C separate signal input RGB or YUV RGB/Color difference decoder PC1830 8-bit A/D PC659A 8 PC1830 2. BLOCK DIAGRAM VCC Sub color control VCC Separate/ composite switch Separate chroma CVBS + Contrast control VCC 3.58/4.43 NTSC/PAL 42 41 VCC + + + Clamp R pulse 23 22 B G + 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 Mode switch Sync. separate Clamp Separate/composite switch, ACC amp. subcolor control Filter f0 adjust 3.58 MHz/4.43 MHz VCXO, PAL SW RGB output buffer R G B C fSC V filter H sync. detect H V chroma trap chroma BPF APC, killer detect, IDENT detect C R-Y, B-Y fSC modulate R-Y B-Y Contrast control NTSC/PAL matrix R-Y B-Y G-Y Separate/composite switch V H BLK Tint control R-Y Killer B-Y H/V count 32 fH VCO Delay Y LPF Y R-Y B-Y Y, R-Y, B-Y output buffer Amp. color control R-Y B-Y AFC wave detect HD, VD, blanking pulse, killer output buffer Y, R-Y, B-Y input clamp 16 17 18 19 20 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 50/60 + + Killer BLK HD detect VD Y R-Y B-Y Y R-Y B-Y Color control VCC + VCC 3 PC1830 3. PIN CONFIGURATION (Top View) 42-pin plastic shrink SOP (375 mil) PC1830GT 32 fH VCO filter 32 fH VCO filter 32 fH VCO filter Horizontal AFC filter GND (synchronous section) fV 50/60 switch Power supply (synchronous section) Color killer output Blanking pulse output HD pulse output VD pulse output Y output R-Y output B-Y output GND (video section) Y input Power supply (video section) R-Y input B-Y input Color control Tint control 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 NTSC/PAL switch fSC switch H sync. detect filter Sync. separation input Contrast control Subcolor control Composite video signal input Power supply (chroma section) Separate chroma input GND (chroma section) ACC filter fo adjustment filter Chroma APC filter fSC VCO input (4.43 MHz) fSC VCO input (3.58 MHz) fSC VCO output Color killer filter B output G output R output Clamp pulse input 4 PC1830 4. PIN EQUIVALENT CIRCUIT DIAGRAMS Pin No. 1 2 3 1 Pin name 32 fH VCO filter Equivalent circuit Function descriptions Pins for connecting a 32 fH oscillation filter. For resonator, use 500 kHz ceramic resonator in both NTSC and PAL modes. Bias of pin 1 is supplied from pin 2 via an external resistor between pins 1 and 2. VCC VCC 2.2 k 2 2.2 k 3.3 k VCC 3 1 mA 4 Horizontal AFC filter Pin for connecting filter of horizontal AFC detector. 300 30 k 3 k VCC 4 5 GND (synchronous section) Synchronous section ground. 5 PC1830 Pin No. 6 Pin name fV 50/60 switch VCC Equivalent circuit Function descriptions Vertical frequency (fV) switch pin. When the pin voltage is 2.2 V or less, the vertical frequency changes to 50 Hz; when 2.8 V or more, to 60 Hz. 20 A 5 k 6 7 Power supply (synchronous section) Synchronous section power supply. 8 Color killer output VCC Color killer output pin. 9 Blanking pulse output 500 Horizontal blanking pulse output pin. 10 HD pulse output 1 k 8 9 10 11 40 k HD pulse output pin 11 VD pulse output 500 VD pulse output pin. 12 Y output Y signal is output. DC level is approx. 2.0 V. VCC 13 R-Y output 12 13 14 2 mA Decoder R-Y and B-Y color difference signal output pins. DC level is approx. 2.5 V. 14 B-Y output 50 15 GND (video section) Video section ground. 6 PC1830 Pin No. 16 Pin name Y input VCC Equivalent circuit Function descriptions Matrix Y signal input pin. This pin also serves as a clamp pin. Input the signal with C coupling. DC level is approx. 2.0 V. 5 k 5 k 16 40 A 17 Power supply (video section) R-Y input VCC Video section power supply. 18 5 k 5 k 19 B-Y input 18 19 40 A Matrix R-Y and B-Y color difference signal input pins. These pins also serve as clamp pins. Input the signals with C coupling. DC level is approx. 2.5 V. Output in PAL mode is "pseud PAL". 20 Color control Pin for color adjustment of matrix circuit. VCC 10 k 40 k 21 Tint control Pin for tint adjustment of matrix circuit. 70 k 20 21 7 PC1830 Pin No. 22 Pin name Clamp pulse input Equivalent circuit Function descriptions Matrix clamp pulse input pin. Clamp operation is performed at 2.8 V or more. VCC 20 A 10 k 22 23 R output VCC 24 G output 23 24 2 mA Matrix R, G, and B output pins. DC level is approx. 2.0 V. Sync. signal component, added to Y-input (16 pin), appears in R, G, and B output pins. 25 B output 25 50 26 Color killer filter Filter connection pin of color killer sync detector. 500 VCC 10 k 10 k 26 27 fSC VCO output VCC 125 125 fSC VCO oscillator output pin. Connect this pin to pin 28 via a 3.58 MHz oscillation filter and to pin 29 via a 4.43 MHz oscillation filter. 3.3 k 27 2.9 mA 8 PC1830 Pin No. 28 Pin name fSC VCO input (3.58 MHz) Equivalent circuit Function descriptions fSC VCO input pins. Connect a 3.58 MHz oscillation filter between pins 27 and 28 and a 4.43 MHz oscillation filter between pins 27 and 29. Switch of pin 28 input and pin 29 input is suppressed in response to pin 41 (fSC switch) voltage. VCC 29 fSC VCO input (4.43 MHz) 5 k 5 k 28 10 k 20 k 0/60 A 60/0 A 20 k VCC VCC 10 k 29 5 k 5 k 80 A 30 Chroma APC filter VCC Pin for connecting filter of chroma APC detector. 500 VCC 5 k 50 k 30 9 PC1830 Pin No. 31 Pin name fO adjustment filter Equivalent circuit Function descriptions Pin for connecting filter of fO automatic adjustment loop. 30 k 500 VCC 31 32 ACC filter VCC 500 Pin for connecting filter of ACC detector. 1 k VCC 5 k 32 33 GND (chroma section) Chroma section ground. 34 Separate chroma input VCC 80 A 30 k 5 k 34 Separate chroma signal input pin. This pin also serves as a separate and composite switch input pin. If the pin voltage is set to 3.7 V or more, composite input mode is entered. 35 Power supply (chroma section) Chroma section power supply. 10 PC1830 Pin No. 36 Pin name Composite video signal input VCC 5 k 5 k 36 Equivalent circuit Function descriptions Composite video signal or separate Y signal input pin. This pin also serves as a clamp pin. Input the signal with C coupling. DC level is approx. 2.3 V. 37 Subcolor control VCC Decoder color and contrast adjustment pins. 10 k 40 k 38 Contrast control 70 k 37 38 39 Sync. separation input VCC Input pin of sync. separation circuit. 5 k 16 k 100 167 5 k VCC 5 k 39 11 PC1830 Pin No. 40 Pin name H sync. detect filter Equivalent circuit Function descriptions Pin for connecting filter of H sync. detector. VCC 1 k 10 k 10 k VCC 40 41 fSC switch VCC 20 A Pin for controlling fSC VCO input (pins 28, 29) switch. When the pin voltage is 2.8 V or more, the mode changes to the 3.58 MHz mode; when 2.2 V or less, to the 4.43 MHz mode. 5 k 41 42 NTSC/PAL switch VCC 5 k 42 5 k 20 A Pin for controlling switch of NTSC and PAL modes of decoder and matrix. One of the following three combinations of decoder and matrix modes can be selected depending on the value of the pin 42 voltage V42: 1. When V42 = 0 V decoder = PAL matrix = PAL 2. When V42 = 2.5 V decoder = NTSC matrix = NTSC 3. When V42 = 5 V decoder = NTSC matrix = PAL 12 PC1830 5. BLOCK OPERATION 5.1 Video Signal Processing Section (1) Input signal After coupling by a capacitor (0.22 F), a 1 Vp-p composite video signal is input to the composite video signal input pin (pin 36). (2) Clamp circuit The clamp circuit controls the pedestal voltage level to be constant to make it a reference voltage for the post-stage signal processing. (3) Chroma trap circuit Eliminates the chroma signal (NTSC system: approximately 3.58 MHz, PAL system: approximately 4.43 MHz) from a composite video signal and extracts a brightness signal. (4) Separate/composite switching circuit Operates as shown in Table 5-1 according to the voltage of the separate chroma input pin (pin 34). Table 5-1. Operation when Switching Separate/Composite Signals Separate chroma input pin (pin 34) voltage Less than 3.7 V 3.7 V or higher Mode Brightness signal processing Without chroma trap With chroma trap ACC amp input Y/C separate input Composite video input Input from separate chroma Input from chroma BPF (5) Delay circuit Compensates for the delay between the brightness signal and chroma signal by delaying the brightness signal. (6) Contrast adjustment circuit Adjusts the amplitude of the brightness signal output from the Y output pin (pin 12) according to the voltage of the contrast control pin (pin 38). The control characteristic is shown in Figure 5-1. 13 PC1830 Figure 5-1. Contrast Control Characteristic (a) NTSC mode 400 mVp-p stair step (composite) input 2 VCC = 5 V 2 VCC = 5 V (b) PAL mode 400 mVp-p stair step (composite) input Y output voltage (Vp-p) Y output voltage (Vp-p) 1 1 0 1 2 3 4 5 0 1 2 3 4 5 Contrast control pin voltage (V) Contrast control pin voltage (V) 5.2 Chroma Signal Processing Section (1) Input signal * Composite video signal input After coupling by a capacitor (0.22 F), a 1 Vp-p composite video signal is input to the composite video signal input pin (pin 36). * Separate chroma signal input After coupling by a capacitor (1000 pF), a chroma signal whose burst signal amplitude is 150 mVp-p is input to the separate chroma input pin (pin 34). (2) Chroma BPF circuit Separates the chroma signal from a composite video signal. (3) Separate/composite switching circuit When the potential of the separate chroma input pin (pin 34) is 3.7 V or higher (in composite mode), switches the ACC amp input from the chroma input pin to the chroma BPF circuit output. Processing of the brightness signal at this time is switched so that it passes through the chroma trap circuit. Operation when switching separate/composite signals is shown in Table 5-1. (4) ACC (Auto Color Control) amplification circuit Extracts the burst signal, detects its level and smoothes the voltage of the ACC filter pin (pin 32) by an external capacitor. This smoothed voltage controls color gain to keep the amplitude of the burst signal constant. 14 PC1830 (5) Subcolor control circuit According to the voltage of the subcolor control pin (pin 37), controls the amplitude of the chroma signal output from the ACC amplification circuit after separating the burst signal from it, and adjusts the amplitude of the color difference signal output from the R-Y output pin (pin 13) and B-Y output pin (pin 14). This controls color density on the screen. The control characteristic is shown in Figure 5-2. Figure 5-2. Subcolor Control Characteristic (a) NTSC mode Color bar (composite, burst: 300 mVp-p) input 3 VCC = 5 V 3 VCC = 5 V (b) PAL mode Color bar (composite, burst: 300 mVp-p) input B-Y output voltage (V) 2 B-Y output voltage (V) 1 2 3 4 5 2 1 1 0 0 1 2 3 4 5 Subcolor control pin voltage (V) Subcolor control pin voltage (V) (6) Chroma APC (Auto Phase Control) circuit Detects the phase difference between the burst signal extracted from the chroma signal and the signal from fSCVCXO and smoothes the chroma APC filter pin (pin 30) using a capacitor. This smoothed voltage is used to control the fSCVCXO oscillation frequency. (7) Killer detection circuit Detects the amplitude of the burst signal and executes a mute on the subcolor control circuit when there is no burst signal, preventing it from outputting a chroma signal to avoid color noise. In this case, the output of the color killer output pin (pin 8) is driven high. The color killer sensitivity is determined by the time constant of a resistor and capacitor connected to the color killer filter pin (pin 26). (8) IDENT detection circuit Performs IDENT detection. With IDENT detection, if an NTSC signal (PAL signal in NTSC mode) is input in PAL mode, the color killer turns on and no chroma signal is output. (9) 3.58 MHz/4.43 MHz VCXO, PAL SW circuit Switches the fSCVCO input pin between pin 28 (for 3.58 MHz) and pin 29 (for 4.43 MHz) by controlling the voltage of the fSC switching pin (pin 41) (2.8 V or higher: 3.58 MHz mode, 2.2 V or below: 4.43 MHz mode) to perform fSC oscillation at 3.58 MHz or 4.43 MHz. VCXO is controlled by the voltage of the chroma APC filter pin (pin 30) smoothed by the chroma APC circuit and its phase is synchronized with the input burst signal. The PAL SW circuit inverts the phase of a signal on the R-Y demodulation axis every 1H by IDENT detection. (10) R-Y, B-Y demodulation circuit Performs demodulation using the chroma signal output from the ACC circuit, an R-Y demodulation axis signal and a B-Y demodulation axis signal output from fSCVCXO, and multiplies R-Y by 1.4 and B-Y by 2.03. 15 PC1830 5.3 Matrix Section (1) Input signal * Brightness input signal After coupling by a capacitor (0.22 F), a brightness signal which has 1 Vp-p of video part is input to the Y input pin (pin 16). * Color difference input signal After coupling by a capacitor (0.22 F), 1 Vp-p R-Y and B-Y signals are input to the R-Y and B-Y input pins (pins 18 and 19). (2) Y, R-Y and B-Y input clamp circuit Clamps Y, R-Y and B-Y signals when the voltage of the clamp pulse input pin (pin 22) is 2.8 V or higher. Input a clamp pulse to the clamp pulse input pin (pin 22) in synchronization with the burst section of an input signal as shown in Figure 5-3. In the application circuit example, adjust the position of the clamp pulse by DELAY (PD4538B external variable resistor: 10 k) and the clamp pulse width by PD (PD4538B external variable resistor: 10 k). Figure 5-3. 22-Pin Input Clamp Pulse Waveform Video signal Burst signal Composite video input Clamp operates at 2.8 V or higher. 22-pin input clamp pulse (3) Amplification color control circuit Adjusts the amplitude of a color difference signal input to the R-Y input pin (pin 18) and B-Y input pin (pin 19) according to the voltage of the color control pin (pin 20). This controls the color density on the screen. When using a matrix, adjust the color density mainly using this color control and fix the voltage of the subcolor control pin (pin 37) at 2 V (TYP.). The control characteristic is shown in Figure 5-4. 16 PC1830 Figure 5-4. Color Control Characteristic (a) NTSC mode 400 mVp-p stair step B-Y input Tint control pin voltage: 2 V 1.0 0.9 0.8 1.0 VCC = 5 V 0.9 0.8 VCC = 5 V (b) PAL mode 400 mVp-p stair step B-Y input Tint control pin voltage: 2 V B output voltage (Vp-p) B output voltage (Vp-p) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1 2 3 4 5 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1 2 3 4 5 Color control pin voltage (V) Color control pin voltage (V) (4) Tint control circuit Controls the phase of a color difference signal whose amplitude is adjusted by the color control circuit, in a range of 45 according to the voltage of the tint control pin (pin 21), and adjusts tint on the screen. Table 5-2 shows the demodulation angle and demodulation ratio in each mode and Figure 5-5 shows the control characteristic. Table 5-2. Demodulation Angle and Demodulation Ratio when Tint Control Pin (Pin 21) Voltage = 2 V (TYP.) Mode NTSC PAL Demodulation angle (R-Y) 105 (TYP.) 90 (TYP.) Demodulation ratio (R-Y/B-Y) 0.75 (TYP.) 0.61 (TYP.) Figure 5-5. Tint Control Characteristic (a) NTSC mode 400 mVp-p stair step R-Y, B-Y input Tint control pin voltage: MAX. +90 VCC = 5 V +90 (b) PAL mode 400 mVp-p stair step R-Y, B-Y input Tint control pin voltage: MAX. VCC = 5 V B demodulation angle (deg) +45 B demodulation angle (deg) 0 1 2 3 4 5 +45 0 0 _45 _45 _90 _90 0 1 2 3 4 5 Tint control pin voltage (V) Tint control pin voltage (V) 17 PC1830 (5) G-Y demodulation circuit Demodulates G-Y using (R-Y)', (B-Y)' which is color difference signal after tint adjustment and the following expression. G-Y demodulation expression: (G-Y) = -0.51 x (R-Y)' - 0.19 x (B-Y)' (6) RGB matrix circuit Adds a brightness signal: Y to each of (R-Y)', (B-Y)' and G-Y to create R, G, and B signals. 5.4 Synchronizing Signal Processing Section (1) Input signal A composite video signal or brightness signal is input to the synchronizing separate input pin (pin 39) at 1 VP-P. (2) Sync. separation circuit Separates the sync. signal from a composite video signal. The slice level can be changed using an external resistor: RX (see Figure 5-6, TYP. = 220 ). The operation of the PC1830 sync. separation circuit is explained below. Figure 5-6 is an equivalent circuit diagram of the PC1830 sync. separation circuit. Figure 5-6. PC1830 Sync. Separate Input Section Equivalent Circuit VCC 5 k 16 k 100 167 TR1 VCC Approx. 2.5 V (when VCC = 5 V) Isp 5 k 39 Co A733 Ix Ro 5 k VCC 1.8 k Rx + In Figure 5-6, the slice level of sync. separation is determined as follows: When a negative sync. video signal is input, charge current ISP flows from the PC1830 to CO so that the synchronization peak (minimum potential) becomes approximately 2.5 V. The voltage of the sync. separate input pin (pin 39) becomes 2.5 V or higher during a period other than the synchronization peak (minimum potential), thus cutting off transistor TR1 (reducing the collector current of TR1). Consequently, a charge in CO is discharged via RO and RX by current IX during this cut-off period. Figure 5-7 illustrates this situation. 18 PC1830 Figure 5-7. Sync. Separation Waveform Charge by ISP Discharge by IX VS T1 (4.7 s) T2 (58.86 s) VS in Figure 5-7 represents the slice voltage and can be expressed in the following expression if it is assumed that CO is sufficiently large, and both IX and ISP are linear. VS = 2.5 x (RX/RO) x (T2/T1) [V] The PC1830 amplifies the part lower than this slice voltage (VS) to perform sync. separation. To determine sync. separation sensitivity, change RX to set VS. Decreasing VS is advantageous for separation of the horizontal sync. part, but disadvantageous for separation of the vertical sync. part. On the contrary, increasing VS may cause a sync. failure (jitter) due to noise (spikes) of the horizontal sync. part. Therefore, it is necessary to optimize the constant in accordance with a signal input. As capacitance CO, select a sufficiently large value compared with the charge/discharge current. However, an excessive value may deteriorate the excessive response characteristic, failing to catch up with drastic APL variations of the input signal. The larger RX, the larger the slice level becomes. However, with large RX if the sync. signal level drops (weak electric field signal, etc.) a video signal may be confused with a sync. signal and sliced, making synchronization unstable (abnormal). Caution Since the measuring circuit uses capacitor coupling for input for ease of measurement, it is susceptible to APL variations. Therefore, when configuring the actual circuit, use a Sync Tip clamp circuit in the stage prior to inputting to the emitter follower to stabilize the synchronization peak potential and this will make the circuit more resistant to APL variations. (3) Vertical filter circuit Separates the vertical sync. signal from the sync. signal separated by the sync. separation circuit. (4) Horizontal sync. detection circuit Detects the presence of a horizontal sync. signal and changes the AFC time constant. (5) AFC detection circuit Performs phase detection on an input sync. signal and fH and outputs the phase difference in voltage. Stops phase detection for 9H of the vertical blanking period. (6) 32fH VCO Controls VCO according to the voltage output by the AFC detection circuit and generates 32fH oscillation clocks. 19 PC1830 (7) Horizontal/vertical counter circuit * Horizontal counter circuit Divides a 32fH signal to generate horizontal timing signals such as HD and BLK signals. * 525/625 counter circuit Performs counting at 4fH and generates a vertical timing signal. Generates VD in 0.75H delay from the falling edge of a vertical sync. signal in an odd field and in 0.75H delay from the falling edge of a vertical sync. signal in an even field. 20 PC1830 6. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = +25 C unless otherwise specified) Parameter Power supply voltage Video input signal voltage Chroma input signal voltage Synchronous separation input signal voltage Control signal voltage Permissible package power dissipation Operating ambient temperature Storage temperature Symbol VCC VIY VIC VIS VIcnt PD TA Tstg Ratings 7.0 VCC VCC VCC VCC 500 (on board, TA = +75 C) -20 to +75 -40 to +125 Unit V V V V V mW C C Caution Even if one of the parameters exceeds its absolute maximum rating even momentarily, the quality of the product may be degraded. The absolute maximum rating therefore specifies the upper or lower limit of the value at which the product can be used without physical damages. Be sure not to exceed or fall below this values when using the product. Recommended Operating Conditions Parameter Power supply voltage Composite video input voltage Separate chroma input signal voltage Synchronous separation input signal voltage Control signal voltage Color difference input voltage Symbol VCC VYC VC Conditions MIN. 4.5 -- -- TYP. 5.0 1.0 150 MAX. 5.5 -- -- Unit V Vp-p mVp-p VS -- 1.0 -- Vp-p Vcont VR-Y VB-Y 0 -- 1.0 VCC V VP-P 21 PC1830 ELECTRICAL SPECIFICATIONS (TA = +25 3 C, VCC = +5 V unless otherwise specified) VIDEO SIGNAL PROCESSING SECTION Parameter Power supply current Video voltage gain Symbol ICC Conditions With no input signal Input signal - Composite fSC PAL or MIN. /Separate (MHz) NTSC - - - 50 TYP. 70 MAX. 90 Unit mA Av(comp) Contrast = max. Stair step 1 (400 mVp-p) Both 3.58/ 4.43 3.58/ 4.43 3.58/ 4.43 - 10.0 12.0 14.0 dB Contrast variable range Video output DC voltage fluctuation when contrast is variable Video frequency characteristics evc Max./min. contrast ratio Stair step 1 (400 mVp-p) Sync. signal (300 mVp-p) only Both - 30 - - 400 dB EOYC Output DC fluctuation, Contrast = max./min. Both - - 0 mV fv1 fv2 fv3 fv4 200 kHz/1.8 MHz gain difference, Contrast = max. 200 kHz/5.5 MHz gain difference, Contrast = max. DC voltage of pin 36 Sine wave 1 (400 mVp-p) Composite 4.43 3.58 - - - - - -4 -5 0 -1 2.1 -2 -3 +2 +1 2.5 0 0 +4 +3 3.0 dB dB dB dB V Separate 4.43 3.58 Video input DC voltage Video output DC voltage EYI EYO Scan period voltage of pin 12 Contrast = max. EYO change when VCC changes from 4.5 to 5.5 V Contrast = max. Sync. signal (300 mVp-p) only Both 3.58/ 4.43 - 1.7 2.0 2.4 V Video output DC power supply voltage fluctuation EYOV Sync. signal ( 300 m Vp-p) only Both 3.58/ 4.43 - - 0 100 mV Video output gain power supply voltage fluctuation AVV Video voltage gain Stair step 1 change when VCC (400 mVp-p) changes from 4.5 to 5.5 V, Contrast = max. Gain difference of 200 kHz/3.58 MHz and 200 kHz/4.43 MHz Contrast = max. Sine wave 1 (400 mVp-p) - - - -0.5 0.0 +0.5 dB Trap attenuation amount dt Composite 3.58/ 4.43 - -20 - - dB Remark For the input signal, see Measuring Input Signal. 22 PC1830 CHROMA SECTION (1/3) Parameter ACC amplitude characteristics Symbol ACC1 Conditions B-Y output level fluctuation. With reference to burst 300 mVp-p. Input signal Composite f S C PAL or MIN. /Separate (MHz) NTSC 4.43 - -2.0 TYP. 0.0 MAX. +2.0 Unit dB ACC2 Color Burst Composite bar 600 mVp-p 2 Burst 30 mVp-p Burst 600 mVp-p Burst 30 mVp-p - -7.0 -3.0 +1.0 dB ACC3 3.58 - -2.0 0.0 +2.0 dB ACC4 - -7.0 -3.0 +1.0 dB ACC5 ACC6 B-Y output level fluctuation. With reference to burst 300 mVp-p. Burst Separate 300 mVp-p Burst 15 mVp-p Burst 300 mVp-p Burst 15 mVp-p 4.43 - -2.0 0.0 +2.0 dB - -7.0 -3.0 +1.0 dB ACC7 3.58 - -2.0 0.0 +2.0 dB ACC8 - -7.0 -3.0 +1.0 dB Color killer setting point eKPC Level at which killer output goes high with burst signal 300 mVp-p set to 0 dB. Level at which killer output goes high with burst signal 150 mVp-p set to 0 dB. B-Y output remaining level when killer output is high. Color killer output level when color killer is ON, IOH = -200 A. Color bar 1 Composite 4.43 PAL -48 -40 -32 dB 3.58 Separate 4.43 3.58 NTSC PAL NTSC -48 -48 -48 -40 -40 -40 -32 -32 -32 dB dB dB eKPS Color killer color remainder eOK Color bar 1 - - - 0 - 50 mVp-p Color killer output, high ECKH - - - - 3.9 4.05 V Color killer output, low ECKL Color killer output level when color killer is OFF, IOL = +200 A. B-Y output level ratio of max./min. subcolor. B-Y output remaining subcolor difference level, Color = min. APC pull-in frequency range when burst chroma frequency changes. (fsc = reference) Calculate from oscillation freq. when APC filter pin voltage is 2.3/2.7 V. - - - - 0.5 0.6 V Subcolor control variable range Subcolor control color remainder eCC Color bar 1 Composite 4.43 - 30 45 - dB eOC Color bar 1 Composite 4.43 - 0 - 50 mVp-p APC pull-in range fSP Color bar 1 Composite 4.43 3.58 PAL NTSC PAL NTSC - - 400 400 400 400 1.0 1.0 600 600 600 600 1.2 1.2 - - - - 1.4 1.4 Hz Hz Hz Hz Hz/mV Hz/mV Separate 4.43 3.58 VCO control sensitivity S - - 4.43 3.58 Remark For the input signal, see Measuring Input Signal. 23 PC1830 (2/3) Parameter VCO free-running frequency PAL mode demodulation ratio NTSC mode demodulation ratio PAL mode demodulation angle NTSC mode demodulation angle Maximum color difference output Symbol fS Conditions VCO oscillator freq. Input signal Sync. signal (300 mVp-p) only Rainbow color bar (300 mVp-p) Composite f S C PAL or MIN. /Separate (MHz) NTSC - 4.43 3.58 Composite 4.43 3.58 - - PAL NTSC 400 400 0.9 0.9 TYP. - - 1.0 1.0 MAX. - - 1.1 1.1 Unit Hz Hz Times Times R-Y R-Y/B-Y output ratio B-Y DP R-Y B-Y DN R-YDP R-Y demodulation angle Rainbow color bar (300 mVp-p) R-YDN eBYM Subcolor = max. Rainbow color bar (300 mVp-p) - Composite 4.43 PAL 85 90 95 deg 3.58 NTSC 85 90 95 deg Composite 4.43 - 1.3 1.6 1.9 Vp-p Color difference output remaining carrier level Color difference output remaining harmonic level Color difference output frequency characteristics eCAR R-Y, B-Y output remaining carrier level - 3.58 NTSC 0 - 100 mVp-p eHAR Output remaining harmonic level, R-Y, B-Y = 1 Vp-p f = 50/500 kHz R-Y, B-Y output level ratio f = 50 kHz/1 MHz R-Y, B-Y output level ratio Subcolor = max. R-Y/B-Y output blank period/scan period DC voltage difference Color bar 1 - 3.58 NTSC 0 - 100 mVp-p fCP Since wave 2 (400 mVp-p) Composite 4.43 3.58 PAL NTSC PAL NTSC PAL -5 -3 0 dB fCS Separate 4.43 3.58 -5 -3 0 dB Blanking stage difference eBLK Burst (300 mVp-p) only - 4.43 - 0 20 mV Line fluctuation EORY Subcolor = max. Burst (300 Scan period DC voltage mVp-p) only difference at every horizontal scanning period of R-Y output EORY R-Y output DC voltage, With no signal B-Y output DC voltage, With no signal - - - 4.43 PAL - 0 20 mV Color difference output pin voltage - 4.43 PAL 2.2 2.5 3.0 V EOBY Color difference output pin voltage fluctuation with power supply fluctuation EORYV EORY change when VCC changes from 4.5 to 5.5 V EOBYV EOBY change when VCC changes from 4.5 to 5.5 V - 4.43 PAL 0 100 mV 0 100 mV Remark For the input signal, see Measuring Input Signal. 24 PC1830 (3/3) Parameter Separate chroma input pin voltage Separate chroma input resistance Separate/composite change threshold voltage Symbol EIC Conditions DC voltage of pin 34 Input signal - Composite fSC PAL or MIN. /Separate (MHz) NTSC Separate - - 1.2 TYP. 1.5 MAX. 1.8 Unit V RIC Calculate from input when EIC EIC + 2 V Voltage of pin 34 at which separate/ composite mode is changed - Separate - - 26 35 44 k EICTH - - 3.58 NTSC 3.1 3.4 3.7 V Remark For the input signal, see Measuring Input Signal. 25 PC1830 SYNCHRONOUS SECTION (1/2) Parameter Sync. separation input DC voltage H sync. pull-in range Symbol EIS Conditions Sync. separation input DC voltage at no signal Frequencies at which horizontal AFC can be pulled, H sync width = 4.8 s Calculated from HD output frequency change when horizontal AFC filter pin voltage changes from 2.9 to 3.4 V, With no signal Difference for 15.680 kHz of HD output frequency, With no signal Change of fH when VCC changes from 4.5 to 5.5 V Composite f S C PAL or Input signal MIN. /Separate (MHz) NTSC - - - - 2.25 400 TYP. 2.55 MAX. 2.85 Unit V fHP Sync. signal (300 mVp-p) only - - - - - Hz Horizontal VCO control sensitivity H _ - - - 1.2 1.5 1.9 Hz/mV Horizontal VCO free-running freq. fH - - - - -200 0 +200 Hz Horizontal VCO free-running freq. fluctuation with power supply voltage fluctuation HD pulse output, high HD pulse output, low HD pulse output width Blanking pulse output, high Blanking pulse output, low Blanking pulse output, width Vertical free-running frequency (in 50-Hz mode) fHV - - - - 0 50 Hz EHDH IOH = -200 A IOL = +200 A Sync. signal (300 mVp-p) only Sync. signal (300 mVp-p) only Sync. signal (300 mVp-p) only Sync. signal (300 mVp-p) only - - - 3.9 4.05 - V EHDL - - - - 0.5 0.6 V tWHD When HD pulse rising, falling is 2.5 V IOH = -200 A IOL = +200 A - - - 3.9 4.4 4.9 s V EBLH - - - 3.9 4.05 - EBLL Sync. signal (300 mVp-p) only Sync. signal (300 mVp-p) only Sync. separate input of 3.5 V - - - - 0.5 0.6 V tWBL When blanking pulse rising, falling is 2.5 V H sync. detect filter pin voltage = 0 V H sync. detect filter pin voltage = 5 V H sync. detect filter pin voltage = 0 V H sync. detect filter pin voltage = 5 V - - - 9.9 10.4 10.9 s Hz fv1 - - - - fH/368 - fv2 - - - - fH/352 - Hz fv3 Sync. separate input of -1 mA - - - - fH/272 - Hz fv4 - - - - fH/288 - Hz Remark For the input signal, see Measuring Input Signal. 26 PC1830 (2/2) Parameter Vertical free-running frequency (in 60-Hz mode) Symbol fv5 Conditions H sync. detect filter pin voltage = 0 V H sync. detect filter pin voltage = 5 V H sync. detect filter pin voltage = 0 V H sync. detect filter pin voltage = 5 V IOH = -200 A IOL = +200 A Sync. signal of 300 mVp-p Sync. signal of 300 mVp-p Sync. separate input of -1 mA Input signal Sync. separate input of 3.5 V Composite f S C PAL or MIN. /Separate (MHz) NTSC - - - - TYP. fH/296 MAX. - Unit Hz fv6 - - - - fH/288 - Hz fv7 - - - - fH/232 - Hz fv8 - - - - fH/240 - Hz VD pulse output, high VD pulse output, low Even field VD pulse output width Odd field VD pulse output width EVDH - - - 3.9 4.05 - V EVDL - - - - 0.5 0.6 V tWVDE - - - - 5.5 - H tWVDO - - - - 6.0 - H Remark For the input signal, see Measuring Input Signal. 27 PC1830 MODE CONTROL SECTION Parameter NTSC/PAL mode switch threshold voltage Symbol EPN1 Conditions Voltage of pin 42 at which both decoder and matrix changes to NTSC or PAL mode simultaneously. Voltage of pin 42 at which only matrix changes to NTSC or PAL mode and decoder remains in NTSC mode. Input current of pin 42. Input signal - Composite f S C PAL or MIN. /Separate (MHz) NTSC - - - 1.37 TYP. 1.67 MAX. 1.97 Unit V EPN2 - - - - 3.03 3.33 3.63 V NTSC/PAL mode switch input pin current Subcarrier frequency switch threshold voltage Subcarrier frequency switch input pin current Vertical frequency switch threshold voltage Vertical frequency switch input pin current IIPN - - - - -0.5 +0.2 +2.0 A ESC Voltage of pin 41 at which fSC 3.58/4.43 mode is changed. Input current of pin 41. - - - - 2.2 2.5 2.8 V IISC - - - - -2.0 -0.2 +0.5 A EFV Voltage of pin 6 at which fV 50/60 mode is changed. Input current of pin 6. - - - - 2.2 2.5 2.8 V IIFV - - - - -2.0 -0.2 +0.5 A NTSC/PAL MODE SETTING SW setting of pin 42 Mode 1 Mode 2 Mode 3 Voltage of pin 42 Lower than EPN1 Between EPN1 and EPN2 Higher than EPN2 Decoder mode PAL NTSC NTSC Matrix mode PAL NTSC PAL VERTICAL FREQUENCY (fV) SWITCHING Voltage of pin 6 Lower than EFV Higher than EFV Vertical frequency fv 50 Hz 60 Hz SUBCARRIER FREQUENCY (fSC) SWITCHING Voltage of pin 41 Lower than ESC Higher than ESC Subcarrier frequency fSC 4.43 MHz 3.58 MHz 28 PC1830 MATRIX SECTION (1/2) Parameter Original color output Y voltage gain Y voltage gain RGB output mutual difference Y voltage gain fluctuation with power supply voltage fluctuation Symbol AY Conditions B output voltage gain. Composite f S C PAL or Input signal MIN. /Separate (MHz) NTSC Y:stair step 2 (1 Vp-p) Y:stair step 2 (1 Vp-p) - - - -2.0 TYP. 0.0 MAX. +2.0 Unit dB AYRGB Mutual difference of R, G, and B output voltage gains. AYV - - - -1.0 0.0 +1.0 dB Difference between B Y:stair step 2 output voltage gain and AY (1 Vp-p) under the same conditions as AY except that VCC = 4.5 V, 5.5 V. 200 kHz/6 MHz B output gain difference. Sine wave 4 (1 Vp-p) - - - -0.5 0.0 +0.5 dB Y frequency characteristics fY - - - 0 -3 -5 dB B output color difference voltage gain Color control variable range AB B output voltage gain. Tint control voltage 2.0 V, Color = max. B-Y: stair step 1 (400 mVp-p) - - - 4.0 6.0 8.0 dB eCM Difference between B output B-Y: stair step 1 gain and AB. (400 mVp-p) Tint control voltage 2.0 V, Color = min. B output remaining color difference level. Tint control voltage 2.0 V, Color = min. B-Y: stair step 1 (400 mVp-p) - - - 35 45 - dB Color control color remainder eOCM - - - 0 5 50 mVp-p Color difference voltage gain fluctuation with power supply voltage fluctuation Color difference freq. characteristics ABV Difference between each B B-Y: stair step output voltage gain and AB 1 under the same condition (400 mVp-p) as AB except that VCC is changed from 4.5 to 5.5 V B output gain difference when freq. changes from 200 kHz to 6 MHz. Tint control voltage 2.0 V, Color = max. B-Y: sine wave 3 (400 mVp-p ) - - - -0.5 0.0 +0.5 dB fB - - - 0 -3 -5 dB Tint control variable range eTMAX. See Note. eTMIN. Color = max. Stair step 1 (400 mVp-p) - - PAL/ NTSC +35 - - - - -35 deg deg Note B demodulation angle B is obtained from B output signal voltages using the following expressions: B1 B demodulation angle B = tan-1 B2 Where, B1: B output signal voltage when signal is input only to R-Y B2: B output signal voltage when signal is input only to B-Y, eTMAX. and eTMIN. are obtained from the B values using the following expressions: eTMAX. = B(4) - B(2), eTMIN. = B(2) - B(10) Where, B(0), B(2), B(4): B values when tint control voltage is 0, 2, 4 V, respectively. Remark For the input signal, see Measuring Input Signal. 29 PC1830 (2/2) Parameter PAL mode demodulation ratio Symbol Conditions Input signal Composite f S C PAL or MIN. /Separate (MHz) NTSC - - PAL 0.50 TYP. 0.56 MAX. 0.62 Unit Times R-Y Tint control = 2 V, Color Stair step 1 B-Y P = max. (400 mVp-p) See Note1. G-Y B-Y P R-YMP G-YMP R-Y B-Y MN G-Y B-Y MN 0.31 85 228 NTSC 0.69 0.35 90 237 0.75 0.39 95 246 0.83 Times deg deg Times PAL mode demodulation angle NTSC mode demodulation ratio 0.22 0.25 0.28 Times NTSC mode demodulation angle Clamp pulse input threshold voltage R-Y input pin voltage B-Y input pin voltage R output pin voltage G output pin voltage B output pin voltage DC difference voltage between R, G, B outputs RGB output DC fluctuation in color control mode R-YMN G-YMN ECLP Note 2 - - - - 100 238 2.1 105 247 2.5 110 256 2.9 deg deg V ERYI EBYI ERO EGO EBO EX-Y Maximum value of difference voltages between ERO, EGO, and EBO - - - - - - - - - - - - - - - - - - - - - - - - 2.1 2.1 1.6 1.6 1.6 2.5 2.5 2.0 2.0 2.0 2.9 2.9 2.4 2.4 2.4 300 V V V V V mV ERGBC Maximum value of ERO, EGO, EBO fluctuation Color control = max./min. Tint control = 2.0 V ERGBT Maximum value of ERO, EGO, EBO fluctuation Tint control = max./typ./min. Color control = max. EYIC EYIT EYI Color control = max./min. Tint control = 2.0 V Tint control = max./typ./min. Color control = max. - - - - - 0 300 mV RGB output DC fluctuation in tint control mode - - - - - 0 300 mV Y input DC fluctuation in color control mode Y input DC fluctuation in tint control mode Y input pin voltage - - - - - 0 300 300 2.4 mV - - - - - 0 mV - - - - 1.6 2.0 V Notes 1. From R, G and B output voltages R1, G1 and B1 when signal is input only to R-Y and R, G, and B output voltages R2, G2 and B2 when signal is input only to B-Y, R, G, B demodulation ratio and demodulation angles are obtained by the following expressions: R-Y B-Y = R12 + R22 B12 + B22 , G-Y B-Y = G12 + G22 B12 + B22 R - Y = -tan-1 G - Y = -tan-1 R2 B1 - tan-1 + 90 R1 B2 G1 - 3G2 B1 - tan-1 + 240 B2 3G1 + G2 2. Clamp pulse input voltage which gets 80 A or more at Y input pin voltage = VCC. Remark For the input signal, see Measuring Input Signal. 30 PC1830 Measuring Input Signal * Stair step 1 400 mVp-p 2 1 Vp-p 400 mVp-p 300 mVp-p 1 Vp-p 300 mVp-p * Sync. signal (300 mVp-p) only 300 mVp-p * Sine wave 1 400 mVp-p 2 400 mVp-p 400 mVp-p 400 mVp-p Sine Wave Mono Tone Sine Wave Mono Tone 3 400 mVp-p 4 1 Vp-p 400 mVp-p 1 Vp-p Sine Wave Mono Tone Sine Wave Mono Tone 31 PC1830 * Color bar 1 2 Variable burst or chroma signal amplitude 1 Vp-p 1 Vp-p Variable burst or chroma signal amplitude * Rainbow color bar (300 mVp-p) Rainbow chroma signal 300 mVp-p * Burst (300 mVp-p) only 300 mVp-p 32 PC1830 Timing chart (horizontal period) 1 s Burst signal Composite video input H sync. output (HD) 4 s Blanking output (BLK) 10 s 33 PC1830 Timing chart (vertical period/standard signal input) Odd field Composite video input H sync. output (HD) Blanking output (BLK) V sync. output (VD) 0.75H Even field Composite video input H sync. output (HD) Blanking output (BLK) 6H V sync. output (VD) 0.75H 1.25H 5.5H Remark H represents horizontal scanning period. 34 7. APPLICATION CIRCUIT EXAMPLE Example 1 Notes 1. Crystal resonator for load of 16 pF. 4.433 619 MHz (PAL) : DAISHINKU CORP. (Type: HC-49/U) 3.579 545 MHz (NTSC) : Toyo Communication Equipment Co., Ltd. (Type: TQC203A-8R) 2. CSB500F23: Murata Mfg. Co.,Ltd. Vcc BNC SEP-C-IN 75 150 75 18 k 0.01 F VCC VCC 1.8 k 1 k 220 pF A733 43 k + 42 41 180 k + Subcolor control 0.1 0.1 F F Contrast 2.2 control VCC F VCC 20 k 20 k Vcc 10 k Vcc + 22 F 1000 pF Note 1 C945 C945 4.7 F 680 + k 1 F 0.1 F 15 pF 15 pF 4.43 MHz 3.58 MHz 0.22 F + 470 F + 15 k 820 30 BNC B-OUT 910 k 470 2.4 k 0.22 F 29 28 27 26 25 24 23 22 68 22 k C945 1 k 220 1 F Vcc C945 0.22 F + 470 F Vcc C945 0.22 F + 470 F BNC R-OUT BNC G-OUT 0.22 F 0.1 F 34 33 0.01 F 40 39 38 37 36 35 32 31 BNC Y-IN 10 k 100 F VCC Mode switch Sync. separate Separate/composite switch, ACC amp. subcolor control 68 Filter f0 adjust 3.58 MHz/4.43 MHz VCXO, PAL SW RGB output buffer + Clamp C chroma BPF APC, killer detect, IDENT detect fSC R B G 75 27 k C945 1 k V filter H sync. detect chroma trap NTSC/PAL matrix V Separate/composite switch V H BLK C R-Y, B-Y fSC modulate R-Y B-Y G-Y killer Tint control 68 H VCC Mode 3 Mode 1 20 k Mode 2 R-Y B-Y Delay Contrast control R-Y B-Y Amp. color control PD 10 k H/V count 32 fH VCO LPF Y AFC wave detect HD, VD, blanking pulse, killer output buffer Y R-Y B-Y Y, R-Y, B-Y output buffer Y R-Y B-Y Y, R-Y, B-Y input clamp 16 17 18 19 20 21 0.1 F 22 F + 180 pF 5.1 k VCC 20 k VCC 1 3.58 MHz FSC 4.43 MHz 270 pF 2 3 4 4.3 k 5 6 7 8 Killer detect 9 10 11 12 13 14 15 0.1 F 16 15 14 13 12 11 10 9 PD4538B 12345678 330 4700 2.2 k pF BLK HD VD 0.22 F VCC 390 pF 500 kHz 2.7 k + 2.2 F Note 2 60 Hz FV 50 Hz + 0.1 F 22 F VCC 0.1 0.22 0.22 F F F 470 pF Delay 10 k 5.1 k VCC + 22 F 0.1 F 20 k Color control 20 k Tint control SEP VCC SEP-SW COMP PC1830 35 36 Example 2 (for NTSC limited use) Notes 1. Crystal resonator for load of 16 pF. 3.579 545 MHz (NTSC) : Toyo Communication Equipment Co., Ltd. (Type: TQC203A-8R) 2. CSB500F23: Murata Mfg. Co.,Ltd. Vcc BNC SEP-C-IN 75 150 75 18 k 0.01 F VCC VCC 1.8 k 1 k 220 pF A733 43 k + 42 41 180 k + Subcolor control 0.1 0.1 F F Contrast 2.2 control VCC F VCC 20 k 20 k Vcc 10 k Vcc + 22 F 1000 pF Note 1 C945 C945 4.7 F 680 + k 1 F 0.1 F 15 pF 3.58 MHz 0.22 F + 470 F + 15 k NC 29 BNC B-OUT 910 k 2.4 k 0.22 F 28 27 26 25 24 23 22 68 22 k C945 1 k 220 1 F Vcc C945 30 0.22 F 0.1 F 34 33 0.01 F 40 39 38 37 36 35 32 31 0.22 F + 470 F BNC G-OUT BNC Y-IN 10 k 100 F VCC Mode switch Sync. separate Separate/composite switch, ACC amp. subcolor control 68 Filter f0 adjust 3.58 MHz/4.43 MHz VCXO, PAL SW RGB output buffer Vcc C945 0.22 F + 470 F BNC R-OUT + Clamp C chroma BPF APC, killer detect, IDENT detect fSC R BG 75 27 k C945 1 k V filter H sync. detect chroma trap NTSC/PAL matrix V Separate/composite switch V H BLK AFC wave detect C R-Y, B-Y fSC modulate R-Y B-Y G-Y Killer Tint control 68 H VCC H/V count 32 fH VCO 20 k R-Y B-Y Delay Contrast control R-Y B-Y Amp. color control PD 10 k Y Y HD, VD, blanking pulse, killer output buffer LPF R-Y B-Y Y R-Y B-Y Y, R-Y, B-Y output buffer Y, R-Y, B-Y input clamp 15 16 17 18 19 20 0.1 F 22 F + 180 pF 5.1 k VCC 20 k VCC 1 2 2.2 k 3 330 4700 pF 4 4.3 k 5 6 7 8 Killer detect 9 10 11 12 13 14 21 0.1 F 0.1 F 16 15 14 13 12 11 10 9 PD4538B 12345678 BLK HD VD 0.22 F 270 pF 390 pF 500 kHz 2.7 k + 2.2 F Note 2 + 0.1 F 22 F VCC 0.22 0.22 F F 470 pF Delay 10 k 5.1 k VCC + 22 F 0.1 F 20 k Color control 20 k Tint control SEP VCC SEP-SW COMP PC1830 Example 3 (for PAL limited use) Notes 1. Crystal resonator for load of 16 pF. 4.433 619 MHz (PAL) : DAISHINKU CORP. (Type: HC-49/U) 2. CSB500F23: Murata Mfg. Co.,Ltd. Vcc BNC SEP-C-IN 75 150 75 18 k 0.01 F VCC VCC 1.8 k 1 k 220 pF A733 43 k + 42 41 180 k + Subcolor control 0.1 0.1 F F Contrast 2.2 control VCC F VCC 20 k 20 k Vcc 10 k Vcc + 22 F 1000 pF Note 1 C945 C945 4.7 F 680 + k 1 F 0.1 F 15 pF 4.43 MHz 0.22 F + 470 F + 15 k 820 30 BNC B-OUT 910 k 470 NC 29 28 68 22 k C945 1 k 220 1 F Vcc 0.22 F 27 26 25 24 23 22 0.22 F 0.1 F 34 33 0.01 F C945 40 39 38 37 36 35 32 31 0.22 F + 470 F BNC G-OUT BNC Y-IN 10 k 100 F VCC Mode switch Sync. separate Separate/composite switch, ACC amp. subcolor control 68 Filter f0 adjust 3.58 MHz/4.43 MHz VCXO, PAL SW RGB output buffer Vcc C945 0.22 F + 470 F BNC R-OUT + Clamp C chroma BPF APC, killer detect, IDENT detect fSC R B G 75 27 k C945 1 k V filter H sync. detect chroma trap NTSC/PAL matrix V Separate/composite switch V H BLK C R-Y, B-Y fSC modulate R-Y B-Y G-Y Killer Tint control 68 H H/V count 32 fH VCO R-Y B-Y Delay Contrast control R-Y B-Y Amp. color control PD 10 k LPF Y Y HD, VD, blanking pulse, killer output buffer AFC wave detect R-Y B-Y Y R-Y B-Y Y, R-Y, B-Y output buffer 12 13 14 15 16 Y, R-Y, B-Y input clamp 17 18 19 20 0.1 F 22 F + 180 pF 5.1 k VCC 1 2 2.2 k 3 330 4700 pF 4 4.3 k 5 6 7 8 Killer detect 9 10 11 21 0.1 F 0.1 F 16 15 14 13 12 11 10 9 PD4538B 12345678 BLK HD VD 0.22 F 270 pF 390 pF 500 kHz 2.7 k + 2.2 F Note 2 + 0.1 F 22 F VCC 0.22 0.22 F F 470 pF Delay 10 k 5.1 k VCC + 22 F 0.1 F 20 k Color control 20 k Tint control SEP VCC SEP-SW COMP PC1830 37 38 Example 4 (When RGB matrix section not used) Notes 1. Crystal resonator for load of 16 pF. 4.433 619 MHz (PAL) : DAISHINKU CORP. (Type: HC-49/U) 3.579 545 MHz (NTSC) : Toyo Communication Equipment Co., Ltd. (Type: TQC203A-8R) 2. CSB500F23: Murata Mfg. Co.,Ltd. BNC SEP-C-IN 75 150 75 18 k 0.01 F VCC VCC 1.8 k 1 k 220 pF A733 43 k + 42 41 180 k + Subcolor control 0.1 0.1 F F Contrast 2.2 control VCC F VCC 20 k 20 k Vcc 10 k Vcc + 22 F 1000 pF Note 1 C945 4.7 F 680 + k 1 F 0.1 F 15 pF 15 pF 4.43 MHz 3.58 MHz + 15 k 820 30 910 k 470 2.4 k 0.22 F 29 28 27 26 25 NC 24 23 22 22 k C945 1 k 220 1 F 0.22 F 0.1 F 34 33 0.01 F 40 39 38 37 36 35 32 31 BNC Y-IN 10 k 100 F VCC Mode switch Sync. separate Separate/composite switch, ACC amp. subcolor control Filter f0 adjust 3.58 MHz/4.43 MHz VCXO, PAL SW RGB output buffer R B G + Clamp C chroma BPF APC, killer detect, IDENT detect fSC 75 27 k C945 1 k V filter H sync. detect chroma trap NTSC/PAL matrix R-Y B-Y G-Y V Separate/composite switch V H BLK C R-Y, B-Y fSC modulate R-Y B-Y Contrast control Killer Tint control R-Y B-Y Amp. color control R-Y B-Y H VCC Mode 3 Mode 1 20 k Mode 2 H/V count 32 fH VCO Delay LPF Y AFC wave detect Y R-Y B-Y HD, VD, blanking pulse, killer output buffer Y Y, R-Y, B-Y output buffer Y, R-Y, B-Y input clamp 15 16 17 18 19 20 21 20 k VCC 1 3.58 MHz FSC 4.43 MHz 270 pF 2 2.2 k 3 330 4700 pF 4 4.3 k 5 6 7 8 Killer detect 9 10 11 12 13 14 BLK HD VD Y R-Y B-Y VCC 390 pF 500 kHz 2.7 k + 2.2 F Note 2 60 Hz FV 50 Hz + 0.1 F 22 F VCC + 22 F VCC 0.1 F SEP VCC SEP-SW COMP PC1830 PC1830 8. OPERATING PRECAUTIONS 8.1 PC1830 External Components (1) Resistors Use E24 series resistors (approximately 5% precision) of 1/4 W or higher. (2) Capacitors * Ceramic capacitors of 1000 pF or below Capacitors used for the time constant circuit. Basically use E12 series (10% precision) ones with the center value = 0 in nominal temperature characteristic. * Ceramic capacitors of 1000 pF or higher Equivalent to capacitors for non-critical time constant circuits and for clamp, and bypass capacitors between power supply and GND. Use E12 series (10% precision) ones. Use a type whose capacitance is not extremely affected by temperature variations (ie. with an excellent temperature characteristic). * Electrolytic capacitors Use E6 series (20% precision) ones. Use ones whose capacitance is not extremely affected by temperature variations (ie. with an excellent temperature characteristic). (3) Crystal resonators Use crystal resonators of 16 pF load type as shown below. * For PAL : 4.433 619 MHz (model name: HC-49/U, manufactured by Kinseki, Ltd.) Communication Equipment Co., Ltd.) Note that use of crystal resonators other than the above may deteriorate electrical characteristics. (4) Ceramic resonators Use ceramic resonators as shown below. * CSB500 F23 (manufactured by Murata Mfg. Co., Ltd.) Note that use of ceramic resonators other than the above may deteriorate mainly electrical characteristics of the sync. section. * For NTSC : 3.579 545 MHz (model name: TQC203A-8R (HC-49/U-10 type), manufactured by Toyo 39 PC1830 8.2 PC1830 Pattern Wiring (1) GND line Solid grounding should be applied to three GNDs: synchronous section GND (pin 5), video section GND (pin 15) and chroma section GND (pin 33). They should not be connected to other digital GNDs except the one point of origin. Use thick connection (thick through hole) for each GND pin of the IC. When an emitter follower circuit, amplifier, etc. is connected to the color difference output stage or RGB output stage, separate the solid ground of the output stage from that of the IC output stage. (2) Power supply line The three analog power supplies, synchronous section power supply (pin 7), video section power supply (pin 17) and chroma section power supply (pin 35) should be independent of each other and unified at the supply source. Ensure that there is no unnecessary routing. Separate the digital section power supply from the analog section power supply and connect them only at one point. (3) Signal line In order to avoid signal cross talk, ensure that the color difference signal line (pins 12, 13, and 14) and RGB signal line (pins 23, 24, and 25) are not placed close to or in parallel with the digital signal line or HD (pin 10), VD (pin 11) and BLK (pin 9) lines, or cross those lines. (4) Placement of peripheral components of each pin Place components which are connected with pins 1, 2, 5, 7, 15, 16, 17, 18, 19, 23, 24, 25, 28, 29, 33, 34, and 35 close to the IC. When the placed components are connected to the power supply line or other lines, route low-impedance lines and make sure that the thickest possible lines are used for connection with the IC pins. 40 PC1830 9. PACKAGE DRAWING 42 PIN PLASTIC SHRINK SOP (375 mil) 42 22 detail of lead end 1 A 21 H I G +7 3-3 J F E C D M M N B K L S42GT-80-375B-1 NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D E F G H I J K L M N MILLIMETERS 18.16 MAX. 1.13 MAX. 0.8 (T.P.) 0.35 +0.10 -0.05 0.1250.075 2.9 MAX. 2.50.2 10.30.3 7.150.2 1.60.2 0.15 +0.10 -0.05 0.80.2 0.10 0.10 INCHES 0.715 MAX. 0.044 MAX. 0.031 (T.P.) 0.014 +0.004 -0.003 0.0050.003 0.115 MAX. 0.098+0.009 -0.008 0.406+0.012 -0.013 0.281+0.009 -0.008 0.0630.008 0.006 +0.004 -0.002 0.031 +0.009 -0.008 0.004 0.004 41 PC1830 10. RECOMMENDED SOLDERING CONDITIONS When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. For more details, refer to our document "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (C10535E). Surface Mount Device PC1830GT: 42-pin plastic shrink SOP (375 mil) Process Infrared ray reflow Conditions Peak temperature: 235 C or below (Package surface temperature), Reflow time: 30 seconds or less (at 210 C or higher), Maximum number of reflow processes: 2 times. Peak temperature: 215 C or below (Package surface temperature), Reflow time: 40 seconds or less (at 200 C or higher), Maximum number of reflow processes: 2 times. Pin temperature: 300 C or below, Heat time: 3 seconds or less (Per each side of the device). Symbol IR35-00-2 Vapor phase soldering VP15-00-2 Partial heating method -- Caution Apply only one kind of soldering condition to a device, except for "partial heating method", or the device will be damaged by heat stress. 42 PC1830 [MEMO] 43 |
Price & Availability of UPC1830
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |